What is the Process of Designing a Chip?
By Thomas Mead
The continual growth of complexity in chip design has revolutionised modern computing, leading to highly specialised hardware. The demand for chips is ever-increasing and more industries are becoming computerised, relying on chips to achieve the greatest level of efficiency. This demand has led to the rapid increase of chip complexity and performance. Modern custom chips often take years to develop, cost millions of pounds and rely on the global supply chain with stages of a chip designed and manufactured in different areas of the globe. This article provides an overview of the chip design flow and covers the procedure of taking initial requirements through to design, testing and finally, manufacturing.
The chip design process starts with an idea from which a potential product can be developed to solve a need. From this design idea, a list of requirements is thought out. These requirements include functionality, modes of operation, cost, speed, power, chip area and other factors. The requirements are expanded into a design specification and block diagram. These requirements are also translated into a high-level performance model, which is tested until it correctly performs all the chip’s functionalities.
Often at this stage, a work plan is also established. A work plan consists of considerations such as scheduling, budgeting and resource management.
At the next stage, the architects evaluate the captured requirements to define the structural outline and principles of the chip. The goal of the architects is to develop a solution that satisfies the whole system. Therefore, lots of design variables must be taken into account. Some key architecture considerations are discussed below.
During architectural development, the functionalities of the chip are partitioned to, determine what the operations of the hardware and the software will be. The system is then further divided into sub-systems and components. Also, the interfaces and protocols within the chip are defined. Any required third-party hardware IP and software drivers are identified at this stage and sourced from suitable vendors. Other factors that must be satisfied within the architecture are performance, power, area, layout, clock frequencies, data flow and cost.
The digital design aims to translate the architecture into a behavioural model of the chip. At this stage, a functional Register Transfer Level (RTL) design is produced. An RTL design is typically captured using a hardware description language, such as VHDL or Verilog, to build a high-level representation of the chip. The RTL design represents how the chip should operate in terms of data flow and logical operations between the memory blocks.
The developed RTL undergoes functional verification; this is the process of confirming the operation and logical behaviour of the chip. The primary methodology to achieve this is by running behavioural simulations on the RTL to ensure the functional correctness of the design. Behavioural simulations include writing and running a series of test vectors to verify the logical behaviour of the chip. The scope of the tests must ensure functional coverage of the design. Any design issues found are identified and sent back to the digital design team for corrections. Once the issues are fixed and all the verification tests are passed, the design is signed off.
Design for Testability
The following stage is Design for Testability (DFT), which involves embedding additional testability features within the hardware. This allows tests to be run to identify hardware production defects. This provides a cost-effective solution to test the chip through additional circuitry. DFT assists the manufacturing process both by rejecting defective chips earlier within the development and by simplifying failure analysis through identifying the probable defective areas.
Next is the physical design stage. This includes mapping the RTL design into physical geometric representations of the electronic components within the chip. The physical design team uses the RTL and constraints, along with a library of available logic gates, to produce a GDSII file of the chip design. This stage requires determining which gates to use, placement of gates in the netlist and routing the wires between them. Constraints are implemented on the physical design that must not be violated to ensure the correct and reliable functionality. The pre-defined design rule constraints imposed on the physical design ensure it satisfies the geometric constraints. Also, the architecture defines optimisation constraints, which includes limits such as area, timing and performance. After the physical design is completed and the constraint checks pass, a GDSII file is produced. A GDSII file contains a binary format representation of the chip design, ready for tape-out. Tape-out is the point at which the GDSII file is sent to the foundry.
The fabrication facility uses the GDSII file to generate a photomask. This is applied under a series of complex steps to manufacture the chip. During fabrication, the design is implemented onto a wafer. This is achieved through a sequence of photolithographic and chemical processes used with the photomask. The wafer is then diced into individual dies of each chip. The individual dies are then packaged, which encapsulates the die in a protective casing ready for use within a product.
Bring-Up and Characterisation
After the chip is manufactured, it is put through bring-up which is, a process of booting and getting the chip to operate. After this, the chip undergoes characterisation. This involves performing a variety of tests on the chip, from simple power-ups to applying complex test patterns to put the device into demanding states. As well as determining any chip issues, the effect of different environmental conditions is also tested. Characterisation defines how it performs in comparison to the specification and identifies any unexpected behaviour. After characterisation, the final stage of the chip design process is chip deployment. This entails ramping up and increasing production.
Giving you a brief overview, this article has detailed the main stages undertaken in the chip design flow. It has described the procedure of taking initial requirements through the design development and implementation, as well as verification and fabrication to produce a chip. In reality, the design process is far more complicated. Typically, each stage is completed by a different team. Certain stages partly run in parallel and often design iterations are passed back-and-forth between them. Another important aspect to mention is that chip design tools are critical within the chip design process.
With the chip design industry continuing to pump out innovative solutions, chip design is currently one of the most complicated feats in engineering. This has resulted in high performing chips, which heavily rely on this chip design flow.