Sondrel can create a custom ASIC to take your product line into its next phase of development or create a flexible System on Chip that can be used for multiple product lines.
Talk to our sales team about taking your FPGA or product concept into a custom silicon design.
As part of our commitment to offering excellent value and a fast time to market, we favour a subsystem re-use approach. As we design, we capture our understanding of discrete subsystems so that they can be redeployed in future designs quickly and with far less effort than when designing from scratch.
The benefits of building a System on Chip using a subsystem are obvious – utilising pre-verified and developed IP blocks gives your design a head-start, saving time and money, whilst enabling you to integrate IP and peripherals that makes your design solution unique.
However, what you don’t want is for the subsystem to throw up any constraints or barriers to your tailored specification – a subsystem needs to work for you, not against you.
The Sondrel engineering team has developed a flexible subsystem model that has addressed traditional difficulties associated with subsystem design. This can form the foundation of your unique product, reducing your design and development timeline without compromising on the specification or quality of your design.
The Sondrel team addresses SoC complexity with a ‘divide and conquer’ subsystem that has been developed to adhere to the following principles. These principles ensure the consistency, flexibility and efficiency of the design and development of your SoC:
- It incorporates blocks implementing a well identified feature.
- It hides significant internal connectivity, SoC glues, registers or pieces of the interconnect.
- The subsytem is ‘atomic’: it does not need to be partitioned (ungrouped) by synthesis.
- It does not contain IPs which need to be placed too far from each other in a SoC floorplan.
- It is designed to offer standard interfaces for integration at the upper level.
- It does not contain SoC specific logic.
The IEEE IP-Xact format utilised in our methodology is also used to automate the task of connecting subsystems together to create a System on Chip (SoC). To do this manually would involve an engineer needing to instantiate each component (subsystem) in the code and connect each wire individually. With IP-Xact the engineering team can significantly speed up the development process by being able to re-generate the SoC top-level code quickly.
Power efficient design enables product owners to extract the maximum value from their silicon investment. It means every square millimetre of the chip area is optimised to deliver the best possible performance or processing speed with the lowest power leakage and residual heat output. Simply put, power efficient design helps you do more with less, and when less is a tiny chip area or an advanced process node this can mean a significant production cost. It stands to reason that if your product is to be created on an advanced process node such as 5nm or 7nm, you want to ensure the maximum return for the substantial investment you will need to make.
Sondrel's focus on power efficient design is based upon a comprehensive and up to date understanding of the best processors, embedded memory components, process nodes and design approaches, as well as the reliability and tolerance ranges for those processes and the foundries that offer them. To be completely certain that your design is based on a thorough exploration and evaluation of all the available possibilities you need to involve architects with a neutral and current market overview. Sondrel provides that certainty.