One of the many things that makes working at Sondrel really exciting is that we are one of the few companies continually pushing the boundaries deep into ever more advanced nodes. As more and more foundries are offering 5nm, we are supporting them with 5nm design work. This builds on us being one of the few design houses to have taped out a number of 7nm designs.
The yellow dots on the timeline indicates the first tape-out time of the respective technology node by Sondrel. Each occurred within a short time of the first availability for silicon production on that node. You can see the “steady march” down the nodes. A Sondrel project in 2019 was confirmed at the time by TSMC as the world’s largest 7nm networking IC for Tier 1 semi.
We are one of the few design companies working on Samsung and TSMC at these advanced nodes. Firstly, because they are invariably extremely large and complex with billions of gates in a design, which requires a large team of extremely experienced design engineers. For example, we recently finished a design on 16nm that required over a hundred people working on it full time for over a year; a resource deployment that would typically only be available within a big Blue-Chip company yet we routinely work on several mega-designs simultaneously. Secondly, we have expertise from several designs at 7nm that gives us a head start on the learning curve of understanding the requirements of 5nm.”
The key driving force to move to the 5nm node is the increase in performance due to the smaller distances increasing the operational speeds. For these leading-edge chips, this increase in performance can justify moving to a smaller node, especially alongside the decreased unit cost associated with reduction in the silicon real estate and the power demand being less for the same functionality.
Continually pushing the boundaries deep into ever more advanced nodes.
An example of the design intricacies of these ultra-small nodes that needs to be understood and allowed for is that the resistance of the metal layers varies from the lower to the upper. In an ideal design, the lower, thinner layers with the higher resistance are used for local/short connections and the mid and high levels for longer distances. However, in the real world, there can be areas of congestion where all the high, fast levels are already fully utilised forcing the tool to use the lower slower layers, causing timing closure issues that have to be addressed in the design.