- BSEE or MSEE with 5+ years experience
- Strong understanding of backend ASIC design flow, hierarchical physical design strategies and methodologies, and deep sub-micron technology issues
- Familiar with EDA tools, SOC-Encounter experience is a must
- Successful track records of taping out complex, 65nm or below SOC chips.
- Design automation and analysis using scripting languages, particular Tcl and Perl
- Solid knowledge on sign-off methodology and EDA tools for STA, Noise, Power, etc.
- excellent verbal and written communication skills in English.
- Strong Project Management Capability. A self-starter that is motivated and a good team leader/player
- Domain expert and be able to training/lead the Teams
-Able to take multi-assignments from different customers/Teams
-Good communication skill and customer development capability
- Development and optimization of high performance and low power SoC physical implementation methodology
- Perform block level and full chip implementation including floor planning, P&R, CTS, timing and power analysis etc.
- Design consulting in customer's offices on physical implementation tasks
- Interfacing with foundry and IP providers on IP imports and test definition
- Leading engineering teams
- Positive and good customer interface