Senior Verification Engineer

Reference: YL/29092017/08

You will be part of a Front-end design/verification team that responsible for the SOC/ASIC products development and verification. You will be working with global teams in Sondrel or customer side on SOC/Subsystem/Block level design verification jobs.

This role would be ideal for an Engineer with 2+ years’ experience and will be based in Xian.

Why work for Sondrel?

• Sondrel’s engineers gain a wealth of experience and exposure to numerous projects, technologies, applications and personal engagements. Applications can include; AI, Automotive, and Internet of Things (IoT)
• Lead some of the most complex designs or learn from other talented engineering capabilities, whilst working on one of the numerous designs in progress at a time
• Become an integral member of a truly global business with excellent opportunities for continued learning and skill development.

Responsibilities:

• Work with architecture/IP designers to get a full deep insight on the DUT.
• SOC/Subsystem/Block level verification plan and test plan.
• Developing/Maintaining verification environment, including testbench setup/maintain, testcase create/triage, regression system, methodology/flow deployment.
• Analyse coverage gaps and devise strategies to fill coverage holes, ensuring on-time RTL freeze and signoff. Should be capable of solving problems of moderate complexity.
• Applies judgment in interpreting results and conducting quantitative analysis.
• Will be engaged in maintaining a high quality in their work.
• May lead or train others on the team.
• Should be capable of deliver assignments on time according to the schedule.
• Should be self-disciplined in executing design tasks.

Skill:

• Complex and large-scale SOC/Subsystem/IP/ASIC Design/Integration/Verification experiences.
• Strong knowledge of ARM Processor or Industry bus standard (PCI-e, HT, USB, AMBA) or Multimedia/Video/GPU/DDR is preferred.
• Good knowledge of UVM/OVM/VMM is a plus.
• Good knowledge of Verilog/C/C++/System C/SystemVerilog.
• Solid background of random techniques, coverage-driven verification environment with SVA/PSL assertions.
• Strong ability of scripting languages such as Perl, Python, Makefile, C Shell. Familiar with EDA tools, i.e. Synopsys VCS, Cadence IUS, Mentor QuestaSim, Spyglass . . .
• Low-power design/implementation/simulation flow with UPF/CPF.
• Strong cooperation skills with global teams and communication skills with the ability to convey complex technical concepts to other design/verification peers in verbal or written form.
• Able to take multi-assignments from different customers/Teams.
  

Qualifications:

• A Bachelor degree in either a relevant subject

Remuneration / Benefits:

• Competitive remuneration and additional benefits including a company financial bonus