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Reference: YL/29092017/05


The candidate will have 5 years' experience in digital ASIC/SOC design verification. The candidate should have good understanding of ASIC/SoC design flow and should have:

It is a plus if the candidate is experienced in one or more of the following:

X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system,

NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design,

clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO),

General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.

The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, to be self-driven, have attention to detail and the capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.


The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.

Job Application Form


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