Come and be a part of our successful international expansion plans! Sondrel, Europe’s leading IC Design company, has now expanded its business footprint into India by opening a design centre in the Hyderabad Madhapur IT Hub. If you are a talented engineering professional with leadership qualities and experience in the semiconductor industry, then please get in touch immediately.
The Senior Engineering Manager will be working alongside the global SoC design team, contributing to complex SOC and Subsystem Verification, whilst motivating the team to perform to agreed deliverables. In addition to this the Senior Engineering Manager will be responsible for the day to day management activities of the team and for hiring and training new employees in line with Sondrel’s aggressive growth plans.
- Bachelors / Masters in Electronics or equivalent.
- Develop, motivate and grow the engineering team;
- Lead a team of Verification engineers at our Hyderabad design centre and work with a cross geographic team of engineering experts based in other Sondrel sites worldwide;
- Develop different Verification platforms in SystemC / System Verilog including utilization of Emulation / Prototyping platforms for verifying next generation distributed cache coherent designs;
- Verify the architecture and performance of designs;
- Work with Architecture and Software teams to ensure that the micro-architecture and design is fully verified / validated across multiple platforms;
- Be responsible for a comprehensive Verification plan and drive the implementation of directed / pseudo-random Verification test cases on multiple platforms including emulation and prototyping platforms;
- Deliver profitable client-based project on time and to customer expectations.
- 14+ total years of experience, including 5+ years' experience in the Verification of SoC / Cache coherent designs;
- Strong foundation in SoC Verification of multi-core cache coherent processors is a plus;
- Experience in distributed cache coherent design Verification like ccNUMA designs is desirable;
- Strong analytical problem solving skills;
- Strong experience in HDL, Verification, and general logic design / verification concepts;
- Expertise in Verilog / System Verilog, C/C++/SystemC, OVM, UVM and scripting languages like Perl / Python, etc.
- Excellent written and verbal communication skills;
- Excellent leadership skills, interpersonal skills & self-initiative.
Remuneration / Benefits:
- Competitive remuneration and additional benefits including a company financial bonus.