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Reference: YL/29092017/06

Job description:

Participate in definition of both chip level and block level design-for-test structure and methodology
Responsible for ATPG and model creation, memory Built in Self Test, Embedded Deterministic Test and Boundary Scan Test
Work closely with design engineer for design optimization for test coverage improvement, test volumn and test time reduction
Responsible for scan pattern simulation based on timing files and gate-level netlist, assist backend engineer with scan chain insertion and timing analysis
Work closely with Product Engineer to debug and solve scan pattern failures on tester
Work as a global team to do complex SOC design and test


Bachelors or Master Degree or University Degree or equivalent from Electronic, Electrical or Computer Science, 5+ years industry experience
Good communication and interpersonal skills
Good language skills in English, with a minimum Pass CET-6
Have knowledge about EDA tools as well as VLSI design flow
Good knowledge in Verilog, VHDL and script language
Has used Unix/Linux system and EDA tools from Cadence, Synopsys, Mentor digital and/or analog developing
Basic knowledge of MBIST, Scan is a plus

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