The RTL2GDS Team Lead is expected to work as part of Sondrel's digital implementation design team providing technical leadership for the SoC.
You will have responsibility for the implementation of the top-level of SoCs, full-chip SoC coordination and sign-off and implementation of hierarchical digital sub-systems.
This role will be based in one of our UK design offices in Bristol, Theale or Kings Langley.
Top-Level implementation and integration of complex, multi-hierarchy SoCs:
- Full chip floorplanning;
- Floorplanning, padring/RDL creation and AMS PHY integration;
- Creation of physical data for hierarchical sub-blocks;
- Full chip placement, CTS, routing, closure and sign off;
- Full chip DRC, LVS, Low Power, IR drop, STA analysis and sign off;
- Coordination and integration of hierarchical sub-blocks begin delivered by design team into the full chip implementation;
Implementation of hierarchical digital design blocks:
- Synthesis, DFT insertion and Place & Route;
- DRC, LVS and DFM analysis and closure;
- IR drop analysis and low power implementation;
- Timing analysis and closure.
Technical coordination of engineering team to ensure delivery and integration of consistent, high quality sub-blocks;
- Provide technical leadership for the physical implementation of the SoC;
- Be pro-active in solving problems both of yourself and others in the team;
- Role model and providing positive influence on the team;
- Contribute to design flow development.
A Masters or PhD in a related subject but with 5 years’ practicable experience is desirable.
Skills and Experience:
Proven track record with the following:
- Full chip implementation and sign off;
- Padring creation and AMS PHY integration;
- Synthesis and P&R using Synopsys toolchain – specifically DC-G and ICC2;
- Hierarchical SoC design including driving and management of the implementation of sub-blocks;
- Full chip signoff with Mentor Calibre;
- Low Power implementation and sign off;
- Full chip timing analysis and closure, including block-block constraint budgeting and timing closure;
- Implementation of complex SoC Network-on-Chip;
- RDL and bump planning, including interacting with package designer;
- SoC tape-outs in TSMC 16nm process.
- Experienced technical lead on hierarchical SoC projects;
- Demonstrates capability as a problem solver;
- Evaluates issues and defines solutions as part of a team or takes the lead in solving issues;
- Interest in digital circuit design at transistor level;
- Knowledge of silicon manufacturing and yield issues;
- Scripting languages (Perl, Tcl, and / or Python).
Remuneration / Benefits:
- Competitive remuneration and additional benefits including a company financial bonus;
- Fantastic opportunity to join a rapidly growing cutting edge design company;
- Excellent training and career-progression opportunities with the option for exemplary candidates to lead and manage their own team.