We are looking for a dynamic and talented engineering manager to manage a team of Sondrel engineers working on high-end peripheral IP and peripheral subsystems for our leading edge SoC developments.
You will be the technical lead and project manager driving through IP development on a range for peripheral designs. This involves working with the team tasked with standard digital peripheral IP design, verification, synthesis, software development, real world validation and silicon characterisation for digital interface IP.
The team are also responsible for the configuration, integration and validation of SerDes based high speed interface IP.
Peripheral IP and subsystem technical lead:
- You will help specify, architect and maintain a wide portfolio of IPs used in Sondrel’s SoCs, including DMA controllers, interconnects, serial audio IPs and peripherals used for low-bandwidth communication, like I2C, SDhost/devices, Parallel and serial NAND and NOR controllers;
- You will manage the development of subsystems for high bandwidth communication, using 3rd party IPs and integrating according to the Sondrel’s SoC design flow. Work with IPs such as USB, SATA, PCIe, and Ethernet.
Leadership and Engagement:
- You will be responsible for the development, training and welfare of a team of hardware engineers;
- You will be managing, coordinating, and interfacing with a team of a further 10-15 engineers working on peripheral projects, consisting of verification, software, and back-end engineers;
- You will be managing peripheral development projects from initial concepts, design, layout and silicon bring-up;
- You will be responsible for project plan development and maintenance to deliver projects on target;
- Interfacing with IP suppliers and customers of IP in SoC projects.
- Should be able to contribute to technical white papers;
- May contribute to sales support as part of a team;
- Should be self-disciplined in executing design tasks.
- Experienced in the full SoC life-cycle from design specification to silicon bring-up;
- VHDL and Verilog;
- Source code control (Perforce or similar);
- Scripting (Perl, Python, AWK, sed or similar);
- Bug tracking;
- CDC, Linting, Formality or similar;
- Logic Synthesis (Synopsys Design Compiler or similar) and timing closure (Synopsis Primetime);
- Knowledge of one or many of the following communication protocols: PCIe, SATA, USB, DDR, Ethernet and AMBA AXI4/ACE protocol and infrastructure;
- FPGA prototyping;
- Project planning tool experience, such as Microsoft project;
- Strong organisational, communication and leadership skills;
- Past experience in complex IP and system development/management, including: Specification / architect, RTL design and verification and System configuration;
- Support or perform SoC level integration and verification.
The ideal candidate will have a degree, masters or PhD in a relevant subject and 7 years' worth of experience.
Remuneration / Benefits:
- Competitive remuneration and additional benefits including a company financial bonus;
- Fantastic opportunity to join a rapidly growing cutting edge design company;
- Excellent training and career-progression opportunities with the option for exemplary candidates to lead and manage their own team.