Purpose of Role
The Senior DFT Design Engineer is expected to work as part of our growing System on Chip design team. The engineer will lead a team of DFT engineers and be responsible for implementation and verification of a full commercial silicon test strategy for complex SoCs. The engineer will also have responsibility for developing advanced Design for Test techniques and be responsible for architecting the DFT strategy on ongoing and future projects.
- Researching leading techniques for efficient, structured test of digital and analogue silicon circuits and adapting them for specific customer requirements to create a clear strategy document.
- Work with both junior and senior engineers to provide them with the direction to achieve the agreed test targets.
- Leading a small group of DFT engineers, planning the remaining work, assigning tasks, managing priorities, reporting progress to the programme manager and to the project manager.
- RTL design, qualification and verification of DFT controllers and associated logic.
- Lead DFT flow development.
- Communicate with the customer to generate an agreed suite of ATE test vectors to take the SoC to production as quickly as possible and be responsible for ATE bring-up.
- Involvement in selecting CAD tools and the deployment thereof to execute the insertion and verification of scan, memory and AMS BIST, memory repair, boundary scan.
- Lead DFT activity on projects with little guidance and have the ability to work independently.
- Solving problems of moderate to high complexity
- Apply judgment in interpreting results and conducting quantitative analysis
- Interact with the more experienced team members to resolve problems.
- Interact with team members from other disciplines to ensure DfT strategy is implemented successfully throughout the design process.
- Work alongside junior members of the team to mentor and coach them in all DfT activities.
- Communication effectively and as required by the Project or Engagement Manager with the customer to set and meet expected and agreed targets.
- Represent Sondrel at conferences and meetings and present technical papers
- A higher degree in a relevant engineering subject.
- Masters or PhD in a related subject but with 5 years practicable experience.
Skills and Experience
- 5+ years’ experience. Guided by program or project objectives
- Unix/Linux environments and associated shell scripting
- VHDL & Verilog RTL coding and debugging techniques
- Experience of architecting complex, hierarchical scan solutions on large SoCs.
- Deep knowledge of the leading EDA vendors’ tool offerings in the fields of scan insertion/simulation, boundary scan and memory BIST/repair.
- Experience of developing ATE test programmes and supporting product engineering teams to bring up and debug these.
- Serves as an independent individual contributor to technical project
- Demonstrates capability as a problem solver with an ability to work individually or as part of a team
- Evaluates issues and defines solutions as part of a team or takes the lead in solving the issue.
- Previous experience in leading a small team of engineers.
- Revision control (CVS, GIT, Perforce etc.)
- Tcl, Perl and or Python
- Good knowledge of design considerations (clock trees, reset networks, timing analysis, constraints generation, synthesis)
- Functional simulation using IUS or VCS.
- Formal Equivalence tools.
- Applies advanced knowledge of a single sub-function OR thorough knowledge of multiple sub-functions
Remuneration and benefits
- Competitive salary
- Annual company bonus
- Flexible working
- 25 days paid annual holiday
- Company pension scheme
- Opportunity to travel both domestically and internationally
- Opportunity for career progression