Staff DfT Engineer
Why work for Sondrel?
- Sondrel’s engineers gain a wealth of experience and exposure to numerous projects, technologies, applications and personal engagements. Applications can include; AI, Automotive, and Internet of Things (IoT)
- Lead some of the most complex designs or learn from other talented engineering capabilities, whilst working on one of the numerous designs in progress at a time
- Become an integral member of a truly global business with excellent opportunities for continued learning and skill development
- At this level the China Senior Staff Engineer Level I (Backend, DFT) should show ability in many tools or be an expert in one or two. Examples of which are: Synthesis, Scan/MBIST/LBIST/BSD insertion, ATPG, Formal verification, Timing
- The person could Follows plans and project steps defined by others, and serves as an independent individual contributor to technical project
- Should be capable of solving problems of moderate complexity independently
- Be able to evaluate issues and define solutions for issue fixing independently
- Will be engaged in maintaining a high quality in their work.
- Should be able to contributes to technical white papers
- Contributes to technical discussions with customers at all stages of sales interaction
- Contributes to the development of technical sales documents such as a Statement of Work
- Listens to customer feedback, recognizes opportunities and provides feedback for technical innovation, and push that into business opportunity with Sondrel Business Team
- Should be capable of deliver assignments on time according to the schedule
- Should be self-disciplined in executing design tasks.
- Should be a team leader to lead some junior engineers to work on customer/internal projects.
- Should be able to take multi-assignments from different customers/Teams
- Typically, 5-7 years’ experience. Guided by program or project objectives.
- Expertise with DFT tools from Mentor, Synopsys, or Cadence:
Scan/MBIST/BSD/LBIST insertion using either Mentor Tessent, Synopsys DC, or Cadence RC;
ATPG using either Mentor Tessent, Synopsys TetraMax, or Cadence ET;
Pattern verification using VCS/NC-Verilog/NC-sim/ModelSim
- Good knowledge of DFT;
- Experience of DFT architecture design
- Serves as an independent individual contributor to technical project
- A degree/masters or PhD in a relevant subject
Remuneration / Benefits:
- Competitive remuneration and additional benefits including a company financial bonus
To apply, please contact and send an e-mail attaching your CV to firstname.lastname@example.org
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