When designing a smartwatch, there are two major constraints – everything has to fit into the wristwatch form factor and the battery life has to be long enough for practical everyday use. A watch that needs recharging partway through the day is a terrible user experience and it was only a few years ago that new display technology dramatically reduced power consumption to enable much longer battery life and then sales rocketed. Always fitting into the same form factor is a huge challenge when the next generation has to have more features to make it smarter and therefore generate sales. An analog watch could last for years but a smart watch only a few before it is replaced by a more feature-rich one.
These two constraints actually play to two of Sondrel’s key strengths – designing for low power operation and designing for minimal area. Laying out all the IP blocks needed for an ASIC is relatively easy at the first pass – it’s rather like putting all the pieces of a jigsaw out on a table top. The skill is connecting them all together in the right locations to optimise the flow of data between the blocks without bottlenecks, and areas of overheating. And the area has to be minimised to keep costs down though this is partially helped (or complicated) by having multiple layers for interconnections making this a three-dimensional challenge. Or four dimensional when you consider timing issues. Fortunately, our engineers love these kinds of challenges.
The ideal solution inside a smartwatch is all the electronics on just one chip rather than numerous chips as they take up much more space -- the sum of ICs being greater than an all-in-one. There are few companies with the skills to design such a complex ASIC which is why we are in discussions with a couple of companies in this area.
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