Today’s SoC designs are complex and require considerable engineering resources and time to design and develop. To reduce the cost and effort, a subsystem approach should be considered.
The benefits of building a SoC using a subsystem are obvious – utilising pre-verified and developed IP blocks gives your design a head-start, saving time and money, whilst enabling you to integrate IP and peripherals that makes your design solution unique.
However, what you don’t want is for the subsystem to throw up any constraints or barriers to your tailored specification – a subsystem needs to work for you, not against you.
The Sondrel engineering team has developed a flexible subsystem model that has addressed traditional difficulties associated with subsystem design. This can form the foundation of your unique product, reducing your design and development timeline without compromising on the specification or quality of your design.
The Sondrel team addresses SoC complexity with a ‘divide and conquer’ subsystem that has been developed to adhere to the following principles. These principles ensure the consistency, flexibility and efficiency of the design and development of your SoC:
- It incorporates blocks implementing a well identified feature.
- It hides significant internal connectivity, SoC glues, registers or pieces of the interconnect.
- The subsytem is ‘atomic’: it does not need to be partitioned (ungrouped) by synthesis.
- It does not contain IPs which need to be placed too far from each other in a SoC floorplan.
- It’s designed to offer standard interfaces for integration at the upper level.
- It does not contain soc specific logic.
The IEEE IP-Xact format, that is utilised in our methodology, is also used to automate the task of connecting subsystems together to create a system on chip. To do this manually would involve an engineer needing to instantiate each component (subsystem) in the code and connect each wire individually. With IP-Xact the engineering team can significantly speed up the development process by being able to re-generate the SoC top level code quickly.
Here is a graphic of the subsystem in action, with customer and third party IP coming together as a system on chip.