Power management techniques for larger SoCs, with multiple heterogeneous processors and complex networks on chip, are largely driven by architectural considerations. 

SoC Architecture

Architectural decisions that allow for the most optimal compute engine for the required software workloads can have a big impact on dynamic power dissipation. Choosing a high-performance processor to run a moderate workload may use higher power unnecessarily. Equally, running demanding workloads on less capable processors can require the processor to be clocked faster than a high-performance processor, using more power. With the correct hardware infrastructure, during the lifetime of an SoC, firmware upgrades can be used to dynamically fine tune power consumption without changing the application software. 

RTL Design

During RTL design, micro-architectural exploration can allow different trade-offs between performance, latency and power consumption, realising efficient implementations for low power applications. Specialist blocks may be designed, as Sondrel has developed in-house, to implement flexible power schemes using a firmware-based power management unit (PMU). This can be used to control the power to supply supplied to different parts of the design depending on the function the design is performing.


Firmware can monitor system performance and determine which processing element should be used for various software processes. Firmware can be used to control dynamic voltage and frequency scaling strategies to increase or decrease the clock and voltage supplies to each-processor. Or software processes can be swapped onto higher or lower performance processors to obtain the most optimal performance/ power trade-off. 
Familiarity with architectural solutions such as the Arm big.LITTLE scheme allow Sondrel Architects to make these kind on trade-offs on your designs today.


At the implementation level we need to have a strategy and objective for both leakage power and dynamic power consumption. This drives foundry and semiconductor process choices as well as more detailed standard cell library choices: for a power managed SoC we might select low power standard cells and perhaps mixed Vt Libraries to optimise both leakage and active power for most cells. In addition, select Low Vt Libraries for clock trees which have high activity to decrease active power at the cost of leakage. Memory choice will be another critical decision as it will probably account for significant leakage power of the SoC and different performance / power trade-off options are available from suppliers.

Clock trees pose a particular challenge as their power can contribute 30-40% of the active power of a design, so use of low power Clock Tree Synthesis (CTS) can have a significant effect.

Power islands with power gating allow independent voltage scaling and power collapsing when an island is idle but require level shifters and clamps at boundaries.
Static voltage scaling cells will allow Firmware to select pre-programmed frequency-voltage pairs to optimise power and performance.

EDA Flows

With low power, EDA flows need to be able to cope with power aware verification and simulation as well as power structure checks; and sign-off for route-ability of multi-mode multi-corner (MMMC) needs to additionally consider power corners. Sondrel has proprietary tool flows for both project management and EDA tools. For EDA flows we are vendor agnostic and can adopt the latest tool advances to complete your design.