Power Integrity Verification

Power Integrity Verification IC Design Services

Modern SoCs are required to make efficient use of the power source to extend battery life or minimize energy requirements. Sophisticated power management strategies such as clock gating, multiple clock and power domains, or dynamic voltage and frequency scaling (DVFS) result in complex on-chip power networks. This adds significant complexity and effort to design verification, which must ensure the device operates correctly in numerous possible power states.

Sondrel’s expertise includes development of the verification plan including suitable coverage of power intent, testbench development, power aware simulation and debug of the most advanced power networks captured in UPF or CPF formats.

What benefits will you see from these services?

Complex SoCs may have a power architecture supporting a number of different power modes, resulting in numerous power states that must be checked to ensure that the device correctly enters and exits each state, and that transitions across power domains within the device are properly managed. The power architecture, describing power and clock domains and the desired power states, can be captured at an abstract level, in UPF format, known as the power intent. This can be simulated along with the RTL providing a reference model that can be used throughout the design cycle to ensure the corresponding power control network is correctly implemented. Being able to simulate the power intent early in the design cycle also enables different power architectures to be explored, in order to identify the preferred solution. The corresponding gate-level representation must also be verified to ensure the power network implementation, including power nets, clock gates, level shifters, state retention cells and isolation cells enable the device to operate correctly in the desired power states. 

Sondrel uses the latest power aware verification methodologies enabling our customers to “shift left”, verifying power architectures early and minimizing bugs occurring in the power control network late in the design cycle. Sondrel is expert in gate-level verification and debug, ensuring the power control network correctly implements the specified power intent.

Process & Methodology

Sondrel power integrity verification services support verification of power control architectures at all stages of the SoC design process from exploration of the power intent through to gate level implementation of the power control network. We have extensive skills in planning, testcase development and debugging at both RTL and gate-level.

Test plans are developed in consultation with the client based on the client’s detailed design specifications, including alignment on key metrics, which are tracked to convey progress throughout the project.

Testcases are developed to test and debug all of the possible power modes, initially using the customers RTL and UPF and then at gate-level when available. The power network can alternatively be verified using the CPF file format if this is the client’s preferred methodology.

Key metrics are analysed and reported throughout the process and our engineers work collaboratively with our customers to resolve any bugs that are encountered.

Download further information on the benefits, engagement models, engineering knowledge and methodology involved in this service in the Power Intergrity Verification Consultancy Datasheet.

ASIC/FPGA Capabilities

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