Functional Verification Services

UVM Testbench : Verification UVM Testbench : Verification

Functional Verification is often the most resource intensive and costly part of the SoC hardware design process. Sondrel’s engineering team can enable your verification environment to “shift left”, starting verification early in the design cycle by streamlining testbench development, facilitating faster turnaround times and high quality, reliable designs.

Sondrel’s expertise covers a comprehensive range of skills including test plan creation, testbench development and design debug at both IP block and SoC level. We are able to bring the latest testbench verification methodologies such as UVM VIP development, ABV and metric driven verification.

What benefits do you gain from these services?

Sondrel provides highly flexible engagement models enabling our clients to choose the optimum way of working for their business. Services are delivered through on-site consultants or at our low cost off-shore design centres, located in EMEA and Asia.

Process & Methodology

Sondrel functional verification services support simulation based verification at all stages of the SoC design process from unit level testing to top-level verification of SoCs. We have extensive skills in planning, testbench development, debugging and porting of legacy verification environments to UVM.

Test plans are developed in consultation with the client, including alignment on key metrics, which are tracked using the latest EDA tools.

Testbenches and test stimuli are constructed to deliver the verification plan using re-usable VIP components, constrained random stimuli or if needed directed tests. Where required, legacy VIP can be ported to UVM to improve re-usability and simulation throughput or assertions created to aid debug. Top-level system tests can be created in SW to verify correct function and performance of specific use cases. Tests may be automated to create regression tests or to aid iterative debugging.

Results of simulations are analyzed and reported. Testcases are refined to achieve coverage goals and our verification engineers collaborate with the designers to resolve any bugs that are encountered, throughout the process.

Download more detailed information on the customer benefits, engagement models, technical details and processes involved in this consultancy service in our Functional Verification Consultancy Datasheet.

ASIC/FPGA Capabilities

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