Formal Verification

Formal Verification Team

How Formal Verification Can Benefit Your SoC

Formal verification is an umbrella term for techniques that use static analysis based on mathematical transformations to determine if hardware or software will behave correctly. This is in contrast to dynamic verification techniques such as simulation that sequentially apply stimuli to a design under test (DUT) and to check the corresponding responses.

Static analysis achieved using formal methods has some advantages. The creation of a traditional testbench to generate and check stimuli is not required. This enables verification of new designs described in HDLs like verilog to begin much earlier whilst the code is evolving, avoiding bugs at source. Complex designs can, in practical terms, simply take too long for the simulator to fully exercise. In this case formal verification can help hunt down bugs not easily debugged with simulation and much faster.

There are many other design issues that cannot be checked using simulation or are less error prone using exhaustive automated checks based on formal methods.

Sondrel’s experts can help you realise the benefits of formal verification to verify designs earlier and more reliably, helping you achieve the desired “shift left”. 

Services can be provided as a fixed price or a time and materials model. Single expert consultancy is also available. Engineers will be based at Sondrel design centres but an on-site at customer presence is also possible. 

Process & Methodology

Sondrel’s consultants will undertake an initial assessment to understand how formal verification can be of most benefit in your environment.

Example services that Sondrel can provide are:

Formal Verification Techniques

 

Read our blog post on Formal Verification Methods and download a datasheet for further details of our service options

Click Here to Download Datasheet

To discuss your project and the best services that suit your project, contact us to speak to one of our experts.

 

ASIC/FPGA Capabilities

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