Verification

Verification Shift Left Services Verification Shift Left Services

Design Verification - 'Shift Left' and Reduce the Risks

Design Verification of modern digital IC’s is challenging, often on the critical path for a project and consuming many costly resources. The consequences of getting this task wrong can have major implications on your business, such as delays in getting your product to market, costly re-spins or even product field failures. It is important to ensure the design has been verified as much as possible within the time and cost constraints of the project. This necessitates starting verification as early in the design cycle as possible, a “shift left” in the verification task, removing hardware and software bugs where they have the least impact. Sondrel’s verification team are skilled in the broad range of advanced design verification and debug methodologies for SoC and IP functional verification with SystemVerilog UVM, power integrity verification, formal verification and HW acceleration enabling your verification projects to “shift left”.

Read more about Paul Martin, who is the Director of Engineering who heads up our Front-End consultancy services, and his engineering team.

You can also read our blog posts on verification strategies and techniques.

Sondrel Blog

 

Sondrel Verification team in Morocco

Contact Sondrel today to discuss the best verification strategy for your IC.

 

Sondrel works with all tool vendors to provide the best solutions for our customers. We participate in the the Mentor Questa Vanguard Program, working in partnership with other industry leading companies to promote comprehensive design and verification solutions.

Mentor Graphics LogoThe Questa Vanguard Program (QVP) extends Mentor Graphics' breadth of design and verification technologies through partnerships with industry-leading companies. QVP partners provide verification related tools and methods, verification IP, conversion services, training and consulting based on Mentor Graphics industry leading Questa verification platform.  The program was established to bring design and verification engineers world-class product integrations and interoperability to enhance their Questa verification options and build a strong and comprehensive SystemVerilog ecosystem.

 

As part of our efforts to deliver a comprehensive 'shift left' consultacy service, Sondrel partners with UltraSoC, who have developed a versatile monitoring and analytics IP that can improve the quality of a design and de-risk the entire development process. This translates into significant benefits for our clients through cost savings and improved design performance. You can find out more about this consultancy service by downloading a technical datasheet detailing the benefits, technical details and delivery process. Monitoring & Analytics IP Hardening Consultancy

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