Sondrel is an ARM Approved Partner
Physical Implementation Capabilities Summary
- Multiple EDA tools support: Mentor, Synopsys, Cadence, Ansys, etc.
- Multiple voltage design
- Complex clocking scheme: clock mesh, multisource
- Flat, virtual flat, hierarchical, chip-assembly flow
- Placement & routing
- Physical verification
- Parasitic extraction
- Static timing analysis
- Advanced STA (MMMC, AOCV, POCV)
- Power verification
- Formal verification
- IR/EM analysis
- ESD and Reliability analysis
RTL2GDSII Design Expertise
Physical Implementation of a large SoC has become increasingly challenging in advance technology nodes. As well as the difficulty of meeting more challenging Performance-Power-Area (PPA) requirements, you have to contend with additional constraints such as On-Chip-Variation (OCV), Design-for-Manufacturing (DfM) and Design-for-Test (DfT). Design teams also have to face the complexity of hierarchical design which may extend to in excess of 100 sub-blocks. Time-to-market is more critical than ever in an extremely competitive marketplace that requires the minimum amount of iterations between design and silicon. As a consequence of all of these challenges, it is vital that the design flow is robust enough to incorporate Engineering-Change-Order (ECO) at the late stage of the project, pre or post manufacturing.
Sondrel addresses the complex requirements of today’s SoC projects by utilising our award winning multi-platform design flow Helium-8P, together with our management methodology Neon, which have both been proven on large designs in sub-deep micro technology nodes, with multiple-location design teams of up to 30 engineers.
IP Hardening Capabilities
Sondrel has been working with IP core providers for many years, having undertaken many core- hardening engagements for a number of leading SoC manufacturers. Sondrel’s position as a key part of the design ecosystem with strong, long-established partnerships with key IC technology suppliers such as ARM, Imagination Technology, Cadence, Ceva, TSMC, Synopsys and Mentor Graphics is very beneficial when completing an IP hardening program which requires inputs from several sources. The company also creates a team of senior engineers experienced in core hardening for every project it undertakes so that each engagement has focus and priority.
Sondrel offers full core hardening processes including:
- Timing, power, and area optimisation
- Low Power place and route optimisation (Vt class mix, clock tree cell type selection, power/area reclaim).
- MV partitioning
- Power switching strategies (peak current analysis)
- Dynamic IR drop/EM fixing
- DFM/Litho-friendly design
Core Hardening Case Study Examples
Sondrel has completed many hundreds of projects, including multiple designs measuring 500mm² or larger. Here are two case study examples involving the hardening of ARM cores:
Following a successful partnership with one of the biggest names in mobile communications that stretches back to cover six previous ARM projects, the customer approached Sondrel to develop a chip for a mobile phone based on two 3.8 million gate A5 cores, using TSMC’s 28nm LP process. The time scale was extremely aggressive, since the customer wished to enter a very competitive market, and the target frequency was a challenging 1GHz at 1.0V. In just three months, Sondrel was able to meet the aggressive target specification, measured under worst-case, industrial conditions and including comfortable allowances for production chip process variations, PLL jitter and On Chip Variation (OCV).
A second example centres around a benchmarking exercise undertaken on behalf of a key partner to evaluate a small number of companies – including Sondrel - in order to understand their capabilities and experience and to see if there is any joint commercial interest. The target was ARM’s highly parallel Mali T264 GPU. Companies taking part in this exercise were rated for speed of achieving the target specification, the power consumed at this specification, and their working style. For this task, Sondrel assigned a senior technical team comprising a mix of on-site and off-site personnel. The team used the company’s Neon Project Management framework to ensure all the sign-off checklist requirements were met and also to provide diligent tracking of the methodology scripts. Neon was also used to create a log book where meeting minutes, working procedures, file systems, flow descriptions and general notes were all managed, ensuring a high quality, low risk, and highly efficient execution.. A weekly update containing risk analysis was presented to the customer. Using this approach, Sondrel was able to achieve the desired performance in just five weeks with just eight iterations – for a project of this complexity, 20 iterations or more is not uncommon. Leakage power – another key consideration in this project - was also significantly reduced. The client was very satisfied with the methodology adopted and the flow of project management information, as well as the final performance of the core.
You can read more detail on our IP Hardening Consultancy Services by downloading a datasheet:
Sondrel IP Hardening of UltraSoC's Monitoring & Analytics IP
In partnership with UltraSoC, Sondrel can deliver real cost savings and improved performance for customers through implementing the soft RTL of UltraSoc's versatile monitoring and analytics IP.
You can find out more by downloading a technical datasheet on the benefits, process and menthodology of this service. Monitoring & Analytics IP Hardening Consultancy
You can access more information on the consultancy services that Sondrel offer in the datasheets prepared by the engineering team.
Advanced Low Power Techniques
Package Substrate Simulations
Designing a SoC for Automotive