FPGA Consulting Services

FPGA Design and Verification Engineers

Sondrel is ready to support you with its expertise in advanced verification methodologies and design techniques for designs targeted for FPGAs. Sondrel’s consultancy services can increase the efficiency and effectiveness of your FPGA design project.

The size of modern FPGAs offer an alternative to an ASIC, where their size and reprogrammability can often lower engineering costs and result in a faster time to market.

Modern FPGA architectures, their complexity and size, offer increasing challenges in design and validation. Without advanced verification techniques such as UVM the ability to prevent and to find critical bugs can be very hard and may lead to many design iterations, increased risk of field failures, field upgrades and higher design costs.

Sondrel’s experience of advanced design and verification methods using UVM, metric driven verification, RTL, synthesis, place and route, STA, can significantly improve the time to market for your FPGA design.

You can download a datasheet summarising our FPGA  services:

FPGA Design & Verification Datasheet

How can you Benefit?

Sondrel uses the latest design knowhow and verification methodologies to help our clients address higher FPGA complexity whilst improving productivity, producing higher quality designs, faster.

Today’s complex FPGAs can support designs similar in complexity to many SoCs and ASICs. The design and verification of these is both resource intensive and time consuming, requiring specialist skills including many more familiar to ASIC experts. Sondrel’s engineers have a wide range of design and verification skills that can address FPGA based designs of all complexities targeted at a variety of market segments including aerospace and automotive.

Sondrel can support your existing approach or enhance your capabilities by providing rapid access to the latest technologies such as ARM processors, on-chip interconnects and high speed interfaces (e.g. DDR, USB, PCIe). Our expertise in advanced methodologies such as synthesis, STA, FPGA place and route, metric driven verification and formal methods increases productivity during FPGA projects and can significantly increase design quality.

Traditional approaches to FPGA verification rely on using simple HDL testbenches and directed tests. The weakness of directed tests for more complex designs is they only cover conditions that have been anticipated by the verifier. Many bugs can slip through and only get identified when the FPGA is running in the lab, where these bugs are difficult to debug and they need to be reproduced in the simulation environment. This iterative approach is very time consuming and high risk. Applying metric driven, constrained random methodologies allow the design to be exercised much more exhaustively with a small set of easily maintainable and reusable tests, ensuring a much more robust design, before FPGA is validated in the lab, minimising the time to debug.

Capabilities Summary

Sondrel can provide these services using our offshore design centers, or on a client site.

Process & Methodology

Specification Planning Phase

Detailed specifications and verification plans are developed and agreed with the customer, along with acceptance tests.

RTL Design

Design specifications are realized in verilog. Where applicable support for power modes can be developed and a complete set of tool constraints used to guide the synthesis, place and route tools are created, ensuring optimal  FPGA performance, utilization and power are achieved

FPGA Implementation

The verilog code is synthesised and mapped onto an FPGA netlist which is mapped onto FPGA IP, logic and routing resources using the FPGA vendors place and route tools.

Verification and Validation

Advanced functional verification techniques are used to verify the Verilog code to high functional and code coverage goals making use of advanced verification technologies like SystemVerilog, UVM and reusable verification IP components. Bugs can be avoided by instrumenting RTL code with assertions that can be used to verify code statically before simulation minimising the number of simulation jobs required to debug the design and reducing time to debug.

Validation of the FPGA design is performed in the lab using board level test methods.

 

Would you like to speak to someone in further detail about how we can support your project? Book a free consultation with us today.

Book a Free Consultation

ASIC/FPGA Capabilities

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